?2010 fairchild semiconductor corporation december 2010 fdp038an06a0 / fdi038an06a0 rev. b2 fdp038an06a0 / fdi038an06a0 fdp038an06a0 / fdi038an06a0 n-channel powertrench ? mosfet 60v, 80a, 3.8m ? features ?r ds(on) = 3.5m ? (typ.), v gs = 10v, i d = 80a q g (tot) = 95nc (typ.), v gs = 10v low miller charge low q rr body diode uis capability (single pulse and repetitive pulse) formerly developmental type 82584 applications motor / body load control abs systems powertrain management injection systems dc-dc converters and off-line ups distributed power architectures and vrms primary switch for 12v and 24v systems mosfet maximum ratings t c = 25c unless otherwise noted thermal characteristics symbol parameter ratings units v dss drain to source voltage 60 v v gs gate to source voltage 20 v i d drain current 80 a continuous (t c < 151 o c, v gs = 10v) continuous (t amb = 25 o c, v gs = 10v, with r ja = 62 o c/w) 17 a pulsed figure 4 a e as single pulse avalanche energy (note 1) 625 mj p d power dissipation 310 w derate above 25 o c2.07w/ o c t j , t stg operating and storage temperature -55 to 175 o c r jc thermal resistance junction to case to-220, to-262 0.48 o c/w r ja thermal resistance junction to ambient to-220, to-262 (note 2) 62 o c/w d g s drain (flange) drain source gate to-262ab fdi series to-220ab fdp series drain drain gate source (flange)
?2010 fairchild semiconductor corporation fdp038an06a0 / fdi038an06a0 rev. b2 fdp038an06a0 / fdi038an06a0 package marking and ordering information electrical characteristics t c = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics (v gs = 10v) drain-source diode characteristics notes: 1: starting t j = 25 c, l = 0.255mh, i as = 70a. 2: pulse width = 100s device marking device package reel size tape width quantity fdp038an06a0 fdp038an06a0 to-220ab tube n/a 50 units fdi038an06a0 fdi038an06a0 to-262ab tube n/a 50 units symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = 250 a, v gs = 0v 60 - - v i dss zero gate voltage drain current v ds = 50v - - 1 a v gs = 0v t c = 150 o c - - 250 i gss gate to source leakage current v gs = 20v - - 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a2-4v r ds(on) drain to source on resistance i d = 80a, v gs = 10v - 0.0035 0.0038 ? i d = 40a, v gs = 6v - 0.0049 0.0074 i d = 80a, v gs = 10v, t j = 175 o c - 0.0071 0.0078 c iss input capacitance v ds = 25v, v gs = 0v, f = 1mhz - 6400 - pf c oss output capacitance - 1123 - pf c rss reverse transfer capacitance - 367 - pf q g(tot) total gate charge at 10v v gs = 0v to 10v v dd = 30v i d = 80a i g = 1.0ma 96 124 nc q g(th) threshold gate charge v gs = 0v to 2v - 12 15 nc q gs gate to source gate charge - 26 - nc q gs2 gate charge threshold to plateau - 15 - nc q gd gate to drain ? miller ? charge - 27 - nc t on tu r n - o n t i m e v dd = 30v, i d = 80a v gs = 10v, r gs = 2.4 ? - - 175 ns t d(on) turn-on delay time - 17 - ns t r rise time - 144 - ns t d(off) turn-off delay time - 34 - ns t f fall time - 60 - ns t off turn-off time - - 115 ns v sd source to drain diode voltage i sd = 80a - - 1.25 v i sd = 40a - - 1.0 v t rr reverse recovery time i sd = 75a, di sd /dt = 100a/ s- -38ns q rr reverse recovered charge i sd = 75a, di sd /dt = 100a/ s- -39nc
?2010 fairchild semiconductor corporation fdp038an06a0 / fdi038an06a0 rev. b2 fdp038an06a0 / fdi038an06a0 typical characteristics t c = 25 c unless otherwise noted figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 0 50 100 150 200 250 25 50 75 100 125 150 175 i d , drain current (a) t c , case temperature ( o c) current limited by package 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 2 t, rectangular pulse duration (s) z jc , normalized thermal impedance notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 duty cycle - descending order single pulse i dm , peak current (a) t, pulse width (s) 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: transconductance may limit current in this region v gs = 10v 10 100 1000 3000
?2010 fairchild semiconductor corporation fdp038an06a0 / fdi038an06a0 rev. b2 fdp038an06a0 / fdi038an06a0 figure 5. forward bias safe operating area note: refer to fairchild application notes an7514 and an7515 figure 6. unclamped inductive switching capability figure 7. transfer characteristics figure 8. saturation characteristics figure 9. drain to source on resistance vs drain current figure 10. normalized drain to source on resistance vs junction temperature typical characteristics t c = 25 c unless otherwise noted 0.1 1 10 100 1000 110100 2000 v ds , drain to source voltage (v) i d , drain current (a) t j = max rated t c = 25 o c single pulse limited by r ds(on) area may be operation in this 10 s 1ms dc 100 s 10ms 1 10 100 0.01 0.1 1 10 100 i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] 0 40 80 120 160 3.0 3.5 4.0 4.5 5.0 5.5 6 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 25 o c t j = -55 o c t j = 175 o c 0 40 80 120 160 0 0.5 1.0 1.5 i d , drain current (a) v ds , drain to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v gs = 5v t c = 25 o c v gs = 20v v gs = 10v v gs = 6v 3 4 5 0 20406080 6 i d , drain current (a) drain to source on resistance(m ? ) v gs = 6v v gs = 10v pulse duration = 80 s duty cycle = 0.5% max 0.5 1.0 1.5 2.0 2.5 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d =80a pulse duration = 80 s duty cycle = 0.5% max -80 -40 0 40 80 120 160 200
?2010 fairchild semiconductor corporation fdp038an06a0 / fdi038an06a0 rev. b2 fdp038an06a0 / fdi038an06a0 figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage figure 14. gate charge waveforms for constant gate current typical characteristics t c = 25 c unless otherwise noted 0.2 0.4 0.6 0.8 1.0 1.2 1.4 v gs = v ds , i d = 250 a normalized gate t j , junction temperature ( o c) threshold voltage -80 -40 0 40 80 120 160 200 0.9 1.0 1.1 1.2 t j , junction temperature ( o c) normalized drain to source i d = 250 a breakdown voltage -80 -40 0 40 80 120 160 200 100 1000 0.1 1 10 60 10000 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 2 4 6 8 10 0 255075100 v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 30v i d = 80a i d = 40a waveforms in descending order:
?2010 fairchild semiconductor corporation fdp038an06a0 / fdi038an06a0 rev. b2 fdp038an06a0 / fdi038an06a0 test circuits and waveforms figure 15. unclamped energy test circuit figure 16. unclamped energy waveforms figure 17. gate charge test circuit figure 18. gate charge waveforms figure 19. switching time test circuit figure 20. switching time waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs + - v ds v dd dut i g(ref) l v dd q g(th) v gs = 2v q gs2 q g(tot) v gs = 10v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0
?2010 fairchild semiconductor corporation fdp038an06a0 / fdi038an06a0 rev. b2 fdp038an06a0 / fdi038an06a0 pspice electrical model .subckt fdp038an06a0 2 1 3 ; rev july 04, 2002 ca 12 8 1.5e-9 cb 15 14 1.5e-9 cin 6 8 6.1e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 69.3 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 lgate 1 9 4.81e-9 ldrain 2 5 1.0e-9 lsource 3 7 4.63e-9 rlgate 1 9 48.1 rldrain 2 5 10 rlsource 3 7 46.3 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 1e-4 rgate 9 20 1.36 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 2.8e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*250),10))} .model dbodymod d (is=2.4e-11 n=1.04 rs=1.65e-3 trs1=2.7e-3 trs2=2e-7 + cjo=4.35e-9 m=5.4e-1 tt=1e-9 xti=3.9) .model dbreakmod d (rs=1.5e-1 trs1=1e-3 trs2=-8.9e-6) .model dplcapmod d (cjo=1.7e-9 is=1e-30 n=10 m=0.47) .model mmedmod nmos (vto=3.3 kp=9 is=1e-30 n=10 tox=1 l=1u w=1u rg=1.36 t_abs=25) .model mstromod nmos (vto=4.00 kp=275 is=1e-30 n=10 tox=1 l=1u w=1u t_abs=25) .model mweakmod nmos (vto=2.72 kp=0.03 is=1e-30 n=10 tox=1 l=1u w=1u rg=13.6 rs=0.1 t_abs=25) .model rbreakmod res (tc1=9e-4 tc2=-9e-7) .model rdrainmod res (tc1=4e-2 tc2=3e-4) .model rslcmod res (tc1=1e-3 tc2=1e-5) .model rsourcemod res (tc1=5e-3 tc2=1e-6) .model rvthresmod res (tc1=-6.7e-3 tc2=-1.5e-5) .model rvtempmod res (tc1=-2.5e-3 tc2=1e-6) .model s1amod vswitch (ron=1e-5 roff=0.1 von=-4 voff=-1.5) .model s1bmod vswitch (ron=1e-5 roff=0.1 von=-1.5 voff=-4) .model s2amod vswitch (ron=1e-5 roff=0.1 von=-1 voff=0.5) .model s2bmod vswitch (ron=1e-5 roff=0.1 von=0.5 voff=-1) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
?2010 fairchild semiconductor corporation fdp038an06a0 / fdi038an06a0 rev. b2 fdp038an06a0 / fdi038an06a0 saber electrical model rev july 4, 2002 template fdp038an06a0 n2,n1,n3 = m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=2.4e-11,nl=1.04,rs=1.65e-3,trs1=2.7e-3,trs2=2e-7,cjo=4.35e-9,m=5.4e-1,tt=1e-9,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.7e-9,isl=10e-30,nl=10,m=0.47) m..model mmedmod = (type=_n,vto=3.3,kp=9,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.00,kp=275,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.72,kp=0.03,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-1.5) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-4) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=0.5) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1) c.ca n12 n8 = 1.5e-9 c.cb n15 n14 = 1.5e-9 c.cin n6 n8 = 6.1e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 69.3 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 4.81e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 4.63e-9 res.rlgate n1 n9 = 48.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 46.3 m.mmed n16 n6 n8 n8 = model=mmedmod, temp=m_temp, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, temp=m_temp, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, temp=m_temp, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=9e-4,tc2=-9e-7 res.rdrain n50 n16 = 1e-4, tc1=4e-2,tc2=3e-4 res.rgate n9 n20 = 1.36 res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.8e-3, tc1=5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-6.7e-3,tc2=-1.5e-5 res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=1e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10)) } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
?2010 fairchild semiconductor corporation fdp038an06a0 / fdi038an06a0 rev. b2 fdp038an06a0 / fdi038an06a0 pspice thermal model rev 23 july 4, 2002 fdp038an06a0t ctherm1 th 6 6.45e-3 ctherm2 6 5 3e-2 ctherm3 5 4 1.4e-2 ctherm4 4 3 1.65e-2 ctherm5 3 2 4.85e-2 ctherm6 2 tl 1e-1 rtherm1 th 6 3.24e-3 rtherm2 6 5 8.08e-3 rtherm3 5 4 2.28e-2 rtherm4 4 3 1e-1 rtherm5 3 2 1.1e-1 rtherm6 2 tl 1.4e-1 saber thermal model saber thermal model fdp035an06a0t template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =6.45e-3 ctherm.ctherm2 6 5 =3e-2 ctherm.ctherm3 5 4 =1.4e-2 ctherm.ctherm4 4 3 =1.65e-2 ctherm.ctherm5 3 2 =4.85e-2 ctherm.ctherm6 2 tl =1e-1 rtherm.rtherm1 th 6 =3.24e-3 rtherm.rtherm2 6 5 =8.08e-3 rtherm.rtherm3 5 4 =2.28e-2 rtherm.rtherm4 4 3 =1e-1 rtherm.rtherm5 3 2 =1.1e-1 rtherm.rtherm6 2 tl=1.4e-1 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case
fdp038an06a0 / fdi038an06a0 8 trademarks the fo llowing includes registered and unregistered trademarks an d service marks, owned by fair child semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive lis t of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairch i ld semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights , nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life suppo rt policy fairchi l d?s products are not authorized for use as critical co mponents in life support de vices or systems without the express written approval of fairchild se miconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a sign ificant injury of the user. 2. a critical component in any compone nt of a life support, device, or system whose failure to perform can be reasonably expe cted to cause the failure of the life suppo rt device or system, or to affect its safety or effectiveness. pr oduct status definitions definition of terms accu po wer? auto-spm? build it now? coreplus? corepower? crossvo lt ? ctl? current t r ansfer logic? deuxpeed ? dual c o ol? ecospark ? e fficentmax? esbc? fairchild ? fair child semi conductor ? fact qui et series? fact ? fast ? fastvcore? fe t bench? flashwriter ? * fps? f-pfs? frfe t ? global power resource sm green fps? gre en fps? e-series? g max ? gto? inte llimax ? isoplanar? megabuck? microcoupler? microfet? micropak? micropak2? millerdrive? motionmax? motion-spm? optihit? optologic ? op top lanar ? ? pdp spm? power - spm? powertrench ? powerxs ? pr ogrammable active droop? qfet ? qs? qu iet series? rapidconfigure? saving our world, 1mw/w/kw at a time? signalwise? smartmax? smart start? spm ? stea lth? su perfet ? supers o t?-3 supersot?-6 supersot?-8 supremos ? syncfet? sync-lock? ?* the power franchise ? the right t e chnology for your success? ? tiny b oost? tinybuck? tinycalc? tinylogic ? tinyopto? tiny power? tin ypwm? tinywire? trifault detect? truecurrent?* ser d es? uhc ? ultra frfet? unifet? vcx? visualmax? xs? ? data sheet i dentification product status definition advance information f ormative / in design datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the ri ght to make changes at any time without notice to improve design. no identification needed full production datasheet contains final spec ifications. fairchild semiconduc tor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specif ications on a product that is discontinued by fairchild semiconductor. the datasheet is for reference information only. anti-counterfeiting policy fairchild se mico nductor corporation?s anti-c ounterfeiting policy. fairch ild?s anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support . counterfeiting of se miconductor pa rts is a growing problem in the industry. all manuf actures of semiconductor products are expe riencing counterfeiting of their parts. customers who inadv ertently purchase counterfeit parts experience many problems such as loss of brand reputation, substa ndard performance, failed application, and increased cost of production and manufacturing delays. fairchild is taking strong measures to protect ourselve s and our customers from the proliferation of counterfeit parts. fairch ild strongly encourages customers to purchase fairchild parts either directly from fa irchild or from authorized fairchild distributors who are listed by country on our web page cited above. product s customers buy either from fairchild directly or fr om authorized fairchild distributors are genuine parts, have full traceability, meet fairchild?s quality st andards for handing and storage and provide access to fairchild?s full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and wi ll appropriately address and warranty issues that may arise. fairchild will not provide any warranty coverage or ot her assistance for parts bought from unau thorized sources. fairchild is committed to combat this global problem and encourage our customer s to do their part in stopping th is practice by buying direct or from authorized distributors. rev. i51 ? ? 20 10 fai rchild semiconductor corporation fdp038an06a0 / fdi038an06a0 rev. b2
|
